1. Field of the Invention
The present invention relates to a fabrication method for a dual damascene structure. More particularly, the present invention relates to a fabrication method for a dual damascene structure comprising an air-gap.
2. Description of the Related Art
The escalating demand of a higher integration in a semiconductor device has led to the development of integrated circuits having multiple levels of interconnects. In such an integrated circuit, the conductive material on one interconnect level is electrically insulated from the conductive material on another interconnect level by a dielectric material.
As the downscaling of the device dimensions continues, the distance between the metal conductive lines also decreases to increase the integration density. A reduced distance between the metal conductive lines, however, generates parasitic capacitance, causing the distributed capacitive load of the metal conductive line to retard the signal propagation. A capacitive coupling between the neighboring metal conductive lines leading to the problem of cross-talk may arise. The generation of the parasitic capacitance, as a result, not only delays the signal propagation of the metal interconnect, but may also cause an unpredictable logic error.